The present invention relates, in general, to vertical field effect transistors. More particularly, the invention relates to vertical field effect transistors with improved commutating safe operating area.
Vertical field effect transistors, also called double diffused metal oxide semiconductor (DMOS) field effect transistors, are well known. DMOS transistors comprise a polysilicon layer formed on a semiconductor substrate and selectively etched to form a polysilicon gate thereby exposing a portion of the substrate. The polysilicon gate is separated from the substrate by a gate oxide layer. For an N-channel device, a P-type base and an N-type source are diffused into the exposed portion of the substrate using the polysilicon gate as a mask, so that a portion of both the source and the base extend beneath the polysilicon gate. A channel region is thus formed beneath the gate between the lateral boundaries of the source and the base. The semiconductor substrate serves as a drain for the DMOS transistor, and is N-type in the case of an N-channel transistor. A gate electrode is formed in contact with the polysilicon gate, and a drain electrode is formed in contact with the substrate. A source electrode is formed in contact with both the source and the base of the transistor.
In normal operation, the channel region is activated by applying charge to the polysilicon gate, which causes an equal and opposite charge to form in the channel region. For the N-channel transistor described hereinbefore, positive charge on the polysilicon gate causes a negative charge layer to form in the channel between the substrate and the source so that current can flow from the drain, through the channel, to the source. When negative charge, or no charge, is applied to the polysilicon gate, current flow through the channel is normally blocked by a PN diode formed between the base and the substrate.
A parasitic bipolar transistor is formed by the source, which acts as an emitter, the base which acts as a base, and the substrate which acts as a collector. The source electrode shorts the base and the emitter of the parasitic transistor, as described hereinbefore. As long as current flow in the base is confined to the channel region, the source electrode effectively prevents turn on of the parasitic transistor. In some applications, however, the PN diode formed by the base and the substrate is forward biased, allowing current to flow from the source electrode, through the base region, to the substrate. In particular, some applications cause the diode to be cycled between a forward bias condition and a reverse bias condition, in which case charge moves from the source electrode to the periphery of the base when the device is switched from forward bias to reverse bias, causing current flow in the base underneath the source. This current flow is necessary to establish a depletion region in the PN diode before the diode can support reverse bias, and is commonly called reverse recovery current. Applications which result in a reverse recovery current are called commutating mode applications. If resistance of the base region under the source is high, the parasitic bipolar transistor will turn on when the reverse recovery current flows, resulting in catastrophic failure of the transistor. Power limitations of the DMOS transistor operating in the commutating mode is hereinafter referred to as commutating safe operating area (CSOA) of the DMOS transistor.
Another problem caused by the parasitic bipolar transistor occurs in applications where the DMOS transistor is required to conduct a large reverse current after the drain-source diode is avalanched. These applications are called unclamped inductive switching (UIS) applications because current is usually caused by avalanching the PN diode while switching an inductive load. Like a CSOA applications, UIS applications result in current flow under the source which can turn on the parasitic bipolar transistor, causing catastrophic failure of the device.
In the past, the problem of the resistance of the base underneath the source was addressed by forming a low resistivity region of the same conductivity type as the base before forming the source so that the low resistivity region was adjacent to the source. The low resistivity region extended vertically beyond the base, so that the reverse recovery current flowed primarily in the low resistivity region instead of the base, due to the lower resistance of the low resistivity region. For the N-channel transistor this low resistivity region is P-type. The source was subsequently formed around the low resistivity region in a ring shape so that a portion of the low resistivity region was exposed in the middle of the source. A source electrode was then formed in contact with the exposed portion of the low resistivity region and the source. This method resulted in a relatively small low resistivity region adjacent to the source due to the limitations of photolithographic processing, and offered limited CSOA improvement. Even when the low resistivity region was doped more heavily, further lowering the resistivity, current flow under the source would turn on the parasitic transistor. Since the junction between the low resistivity region and the substrate determined the breakdown voltage of the transistor, lowering the resistivity to improve CSOA had a negative side effect of reducing breakdown voltage.
More recently, a method was disclosed wherein the low resistivity region was formed using a phosphosilicate glass (PSG) sidewall spacer formed on an edge of the polysilicon gate. In this method, the low resistivity region was formed using the PSG sidewall spacer as a mask, and the phosphorous in the PSG diffused into the silicon during thermal processing to form the source. Using this method, the low resistivity region was self aligned to the polysilicon gate so that only a small portion of the source extended beyond the low resistivity region. A device of this type was described by Mutsushio Mori et al in "An Isolated Gate Bipolar Transistor with a Self Aligned DMOS Structure", IEDM 88-813, 1988. This method, though offering somewhat improved CSOA performance, has limited application because the PSG sidewall spacer could not be removed without damaging the gate region, and it was undesirable to leave the PSG sidewall spacer in the device as it resulted in corrosion of the source electrode which was in contact with the oxide sidewall spacer.
Another method has been used in which the source region and the base region are etched so that a portion of each region is exposed at the surface, and a source electrode is formed in contact with the exposed portions. Such a method is shown in U.S. Pat. No. 4,748,103 issued to Theodore Hollinger on May 31, 1988. This method improves CSOA performance by providing a large area metal contact which extends into the base region deeper than, but still adjacent to, the source. The silicon etching process used to contact the base and source regions can create surface damage, which degraded device leakages. Although this structure provided a smaller area under the source which was exposed to reverse recovery current, it did not seem to solve the problem of bipolar turn on when current did flow under the source.
Another device, described in U.S. Pat. No. 4,587,713 issued to Goodman et al., comprises a low resistivity region which is formed at the same time as the source, using the same mask. In this device, the low resistivity region necessarily underlies all of the source, and extends laterally beyond the source so that a portion of the low resistivity region is provided under the channel. While this device directly addresses the issued of high base resistance under the source, it relies on a deep boron implant having a very narrow distribution to ensure that the low resistivity region does not diffuse into the channel. When the low resistivity region extends into or very near the channel, threshold voltage of the field effect transistor increases, and becomes very difficult to control. Thus, this boron implant and subsequent diffusion make the device difficult to manufacture.
Accordingly, it is an object of the present invention to provide an improved method for making a vertical field effect transistor.
Another object of the present invention is to provide a vertical field effect transistor with improved unclamped inductive switching performance.
It is a further object of the present invention to provide a vertical field effect transistor with improved commutating safe operating area (CSOA).
It is a further object of the present invention to provide a vertical field effect transistor having a low resistivity region underneath a source.
It is a further object of the present invention to provide a method for making a vertical field effect transistor having both high breakdown voltage and improved CSOA performance.
It is still a further object of the present invention to provide a method for making a vertical field effect transistor which does not require silicon etching.
It is another object of the present invention to provide a vertical field effect transistor having improved CSOA performance which does not require additional mask steps.
It is a further object of the present invention to provide a vertical field effect transistor which can be mass produced with little variability in performance.
It is another object of the present invention to provide a method for manufacturing a vertical field effect transistor having improved CSOA performance and a high degree of threshold voltage control.